Fast FIR Algorithm for Area Efficient Parallel Digital Filter Structure for Symmetric Convolution

Authors:PADMA SILIVERI, MD.HAMEED PASHA

0504-0507

Design and Implementation of Fault Tolerant Carry Skip Adder or Subtractor using Reversible Logic Gates

Authors:DONDAPATI NARESH, V.B.GOPALA KRISHNA

0508-0511

Memory Testing using March C-Algorithm

Authors:M.MAMATHA, M.MURALIDHAR

0512-0517

Memory Efficient and High Speed Fir Filter using Distributed Arithmetic

Authors:D.NAGACHANDRIKA, A.RAJESH

0518-0523

FPGA Based Wireless Mobile Jammer

Authors:HAMEED MOHAMMED, V. PRATHYUSHA, K. ASHOKE BABU

0524-0529

An On-Chip Implementation of High Speed Switch Architecture

Authors:V.MADHURI, NERELLA VINOD KUMAR

0530-0536

Design of 32-bit Unsigned Multiplier using CSLA, CLAA, CBLA Adders

Authors:CH.BHAVANI, MURALI KRISHNA

0537-0541

Implementation of Power and Speed Optimized Vedic Multipliers using Reversible Gate Approach

Authors:V.MALLIKARJUNA RAO, NUNNA NARAYANASWAMY

0542-0548

Design of Dual Dynamic Node Hybrid Flip Flop with Embedded Logic Design

Authors:I. SINDHURA, D.SUDHAKAR

0549-554

Designing of 32-Bit CRC Generation for 64-Bit Data

Authors:BAVANDLAPALLI MANOHAR, R.RAMESH BABU

0555-0559